AI-assisted chip design

In plain language

A modern chip holds billions of transistors and a smaller number of large blocks, such as memory banks, that must be placed on the silicon before the wires between them are routed. Where these blocks sit affects how much power the chip uses, how fast it runs and how much space it needs. Engineers have traditionally made these choices with experience and with software that tries many layouts.

In 2021 Google researchers published a paper in Nature proposing that reinforcement learning, a method in which software improves by trial and error, could place these blocks. Synopsys and Cadence sell commercial design tools that use AI to search design options. Both companies report large gains, but those figures come from their own announcements. Academic researchers have questioned whether Google's method beats strong traditional techniques.

Technical explanation

Macro placement, the step where large hard blocks such as memory macros are positioned, is one part of floorplanning. The 2021 Nature paper by Mirhoseini and colleagues proposes a graph placement methodology that uses a learned policy to place these blocks. An addendum to that paper was published in Nature on 26 September 2024. The original developers' 2024 rebuttal says AlphaChip has been widely adopted, and the updated 2023 assessment by Cheng and colleagues refers to an AlphaChip release. These adoption claims are the developers' own and have not been checked independently.

Commercial tools take a different route. Synopsys describes DSO.ai as an autonomous system that searches design spaces to find better power, performance and area results. Cadence describes Cerebrus as having a reinforcement learning engine that automatically optimises tool and chip design options. Cheng and colleagues, in their updated assessment, measure post-route power, performance and area with a commercial tool, which is one way to check a placement after the wiring is complete.

The main technical dispute concerns how the Nature method was tested. Cheng, Kahng, Kundu and colleagues built a stronger simulated annealing baseline using a go-with-the-winners metaheuristic and multi-threading, and released public benchmarks, including sub-10nm designs. Their updated assessment says that the scalability and pre-training claims remain unconfirmed. Goldie, Mirhoseini and Dean's 2024 rebuttal argues that the critics did not pre-train the method, did not train to convergence, used about 20 times fewer experience collectors and half as many GPUs, and tested on cases the authors say are not representative of modern chips. These are the rebuttal's own statements about the critics' work and have not been independently checked.

What the evidence says

Each statement is typed by the strength of its evidence and linked to the source that supports it.

Limitations and open problems

• The central performance claims of the 2021 Nature method are disputed. An ISPD 2023 reassessment by Cheng and colleagues compared it with a stronger simulated annealing baseline, and the 2024 rebuttal by the original developers argues that the critics did not run the method as described.
• Pre-training and scalability of the learned placer remain unconfirmed according to the updated Cheng and colleagues assessment.
• The commercial figures from Synopsys and Cadence come from company releases and selected customers, with different designs and baselines, so they cannot be compared directly with each other or with the Nature results.
• The reported gains are for specific blocks or designs. The Cadence figures, for example, apply to one MediaTek SoC block and one Renesas CPU design, and the Synopsys figures are aggregates of customer results that Synopsys did not independently verify.
• Reproducibility is hard. Results depend on compute budget, training time and the choice of benchmarks, and the rebuttal and critics disagree on what fair testing requires.

Possible future uses

Timeline

1. 9 Jun 2021Mirhoseini and colleagues publish 'A graph placement methodology for fast chip design' in Nature, volume 594, pages 207-212. Sources: [1]
2. 13 Jun 2022Cadence announces that MediaTek and Renesas have used its Cerebrus tool on designs, with results reported by Cadence. Sources: [7]
3. 7 Feb 2023Synopsys announces that customers have registered the first 100 commercial tape-outs using DSO.ai. Sources: [6]
4. 26 Mar 2023Cheng, Kahng, Kundu, Wang and Wang publish 'Assessment of Reinforcement Learning for Macro Placement' at the 2023 International Symposium on Physical Design. Sources: [4], [5]
5. 26 Sept 2024Nature publishes an addendum to the 2021 graph placement paper online. Sources: [2]
6. 15 Nov 2024Goldie, Mirhoseini and Dean post 'That Chip Has Sailed' on arXiv, a rebuttal of the critics of the 2021 method. Sources: [3]

Futures this could help bring about

How far away?

Computer chips designed mostly by AI

Pilots · 2 of 6 steps done

Glossary

Floorplanning

Deciding roughly where the major blocks of a chip will sit before the detailed wiring is designed.

Macro

A large, pre-designed block on a chip, such as a memory bank, that is placed as a single unit.

Tape-out

The point at which a finished chip design is sent to manufacturing.

Simulated annealing

A search method that gradually reduces random changes to find a good arrangement, used as a baseline for chip placement.

Sources

1. peer reviewed paper
   A graph placement methodology for fast chip design
   Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan et al.. Nature, 9 Jun 2021. DOI: 10.1038/s41586-021-03544-w. Accessed 22 Oct 2026.
2. peer reviewed paper
   Addendum: A graph placement methodology for fast chip design
   Anna Goldie, Azalia Mirhoseini, Mustafa Yazgan et al.. Nature, 26 Sept 2024. DOI: 10.1038/s41586-024-08032-5. Accessed 22 Oct 2026.
3. preprint
   That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design
   Anna Goldie, Azalia Mirhoseini, Jeff Dean. arXiv, 15 Nov 2024. Accessed 22 Oct 2026.
4. conference paper
   Assessment of Reinforcement Learning for Macro Placement
   Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu et al.. Proceedings of the 2023 International Symposium on Physical Design, 26 Mar 2023. DOI: 10.1145/3569052.3578926. Accessed 22 Oct 2026.
5. preprint
   An Updated Assessment of Reinforcement Learning for Macro Placement
   Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu et al.. arXiv, 21 Feb 2023. Accessed 22 Oct 2026.
6. company announcement
   AI-designed Chips Reach Scale with First 100 Commercial Tape-outs Using Synopsys Technology
   Synopsys (PR Newswire), reprinted by I-Connect007, 7 Feb 2023. Accessed 22 Oct 2026.
7. company announcement
   Cadence Cerebrus Delivers Transformative Results on Next-Gen Designs
   Cadence Design Systems, reprinted by I-Connect007, 13 Jun 2022. Accessed 22 Oct 2026.

Revision history

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