Chiplets and advanced chip packaging

Also known as Chiplets, Chiplet packaging, Advanced packaging, Multi-die processors

Chiplet designs build a processor from several smaller silicon dies joined by advanced packaging, which can make large designs easier to manufacture and reuse. The joins add cost, heat and capacity limits, and standards such as UCIe and packaging routes from TSMC and Intel are moving the approach into commercial products.

CommercialDemonstratedReviewed 21 Oct 2026
AI illustration · Illustrative scene, not a photograph of the specific device or experiment.

In plain language

Many modern processors are no longer one large piece of silicon. Instead, a designer splits the work into several smaller pieces, called chiplets, and places them side by side or stacked on a shared base. Each piece can be made separately, tested, and then joined to the others with a dense set of tiny electrical connections, so the finished package works much like a single processor.

Splitting a design this way can make manufacturing easier. Large chips are harder to make without a fault somewhere on the silicon, so a smaller piece is more likely to come out working. Makers can test each piece and combine only the good ones. The price is that the joins need advanced packaging, which adds cost, uses up manufacturing capacity, and needs careful design of the power, data links and heat flow.

Technical explanation

Chiplet designs connect dies through die-to-die interfaces. The UCIe 1.0 standard, reported in trade press in April 2022, defines a physical layer, die-to-die protocols and a software stack, and it builds on the PCIe and CXL standards. UCIe 2.0, released in August 2024, adds support for 3D packaging. The UCIe Consortium says this update promises higher bandwidth density and power efficiency, but the coverage reviewed for this profile gives no verified figures for bandwidth per millimetre or per square millimetre. Packaging falls into 2.5D approaches, where chiplets sit side by side on a silicon bridge, interposer or redistribution layer, and 3D approaches, where dies are stacked vertically. TSMC's CoWoS family is another 2.5D route.

Stacking dies vertically creates heat problems. In a 2020 thermal study of a 3D-stacked commercial microprocessor, naive stacking raised the maximum die temperature by up to 12 °C above the 2D design under a worst-case workload, and a logic-over-memory partition roughly halved that increase. Heat has to leave a stack through thinned layers, which limits lateral spreading. The economic case rests on yield. A 2022 cost model by Feng and Ma (DAC 2022) treats re-partitioning a monolithic system into chiplets as a way to raise die yield and lower cost, and it concludes that total system cost can fall with an appropriate multi-chiplet architecture. Their abstract gives no numerical results, so the size of the saving depends on assumptions the sources here do not verify.

Capacity is a separate constraint. TrendForce reported in January 2025 that industry sources estimated TSMC's CoWoS monthly capacity could reach a record 75,000 wafers in 2025, nearly double 2024 levels. The same report relays that TSMC's C.C. Wei acknowledged the capacity "has been facing short supply". Later forecasts disagree, so no single capacity figure is firm.

What the evidence says

Each statement is typed by the strength of its evidence and linked to the source that supports it.

Reported, unverified Stated by a company or team but not independently confirmed.

Trade press reports that UCIe 1.0 defines a die-to-die interconnect covering the physical layer, die-to-die protocols and a software stack, building on PCIe and CXL.

Sources: [1] · Scope paragraph · medium confidence

The UCIe Consortium says UCIe 2.0 adds enhancements for 3D packaging and promises higher bandwidth density and power efficiency; the coverage reviewed gives no figures.

Sources: [2] · Release text · medium confidence

Industry sources estimate that TSMC's CoWoS monthly capacity could reach a record 75,000 wafers in 2025, nearly double 2024 levels.

Sources: [3] · Article body · medium confidence

TrendForce reports, in a paraphrase relayed from an industry report, that TSMC's C.C. Wei acknowledged CoWoS capacity has been facing short supply, and that TSMC is aiming for supply and demand balance in 2025 to 2026.

Sources: [3] · Article body · medium confidence

In a thermal study of a 3D-stacked commercial microprocessor, naive stacking raised peak die temperature by up to 12 °C above the 2D design under a worst-case power-indicative workload, and logic-over-memory partitioning cut that increase by half.

Sources: [5] · Abstract · medium confidence

Proposed A design or plan that has not yet been built or tested.

Feng and Ma build a quantitative cost model for multi-chip integration and conclude that total system cost can be reduced through an appropriate multi-chiplet architecture; the abstract gives no numerical results.

Sources: [4] · Abstract · medium confidence

Limitations and open problems

  • Chiplet yield and cost gains depend on defect density, die size and the cost of testing known good dies. The sources reviewed for this profile give no verified yield or cost figures for a packaged product.
  • Stacked dies have a poorer vertical heat path than a single die. The 2020 microprocessor study found a rise of up to 12 °C for naive stacking, and logic-over-memory partitioning roughly halved it, but that study covers one design only.
  • Advanced packaging capacity has been short. TrendForce's 2025 figures are industry estimates, and forecasts for later years differ.
  • UCIe 2.0 is described as offering higher bandwidth density, but the sources opened for this profile give no verified per-millimetre or per-area figures, so no bandwidth numbers are stated here.
  • Die-to-die links use power and silicon area. The consortium's power-efficiency claim for UCIe 2.0 is not quantified in the sources reviewed.

Possible future uses

Speculative

Ideas, not predictions. None of these has been demonstrated.

  • Placing memory stacks directly on logic dies to shorten data paths in AI accelerators.
  • Co-packaged optical chiplets that place photonic links beside processor dies to cut electrical link power.
  • Libraries of tested chiplets that a company could reuse across several products, rather than designing each chip from scratch.

Timeline

  1. 31 Jul 2020A thermal study of a 3D-stacked commercial microprocessor reports up to 12 °C higher peak die temperature for naive stacking, roughly halved by logic-over-memory partitioning. Sources: [5]
  2. 23 Mar 2022Feng and Ma post the Chiplet Actuary cost model, later presented at DAC 2022, on quantifying the cost of multi-chip integration. Sources: [4]
  3. 11 Apr 2022UCIe 1.0 is reported as a formal die-to-die chiplet standard covering the physical layer, protocols and software stack. Sources: [1]
  4. 1 Aug 2024UCIe Consortium press release dated 1 August 2024 announces UCIe 2.0, adding enhancements for 3D packaging. Sources: [2]
  5. 2 Jan 2025TrendForce reports industry estimates of a record 75,000 TSMC CoWoS wafers per month in 2025, nearly double 2024. Sources: [3]

Futures this could help bring about

AI illustration
How far away?

Chips made with the next generation of EUV machines

Pilots · 5 of 9 steps done

AI illustration
How far away?

Computers built from mix-and-match chiplets

Engineering prototypes · 4 of 7 steps done

Glossary

Chiplet
A small, separately made piece of silicon that is joined with other pieces to form one processor or system.
Known good die
A chip that has been tested and confirmed to work before it is joined into a larger package.
Hybrid bonding
Joining two chips with direct copper-to-copper contacts instead of solder bumps, which allows much finer connections.
Interposer
A base layer, usually silicon, that carries the wiring between chips placed on top of it in a package.

Sources

  1. news
    Chiplets Get a Formal Standard with UCIe 1.0
    Gary Hilson. EE Times Asia, 11 Apr 2022. Accessed 21 Oct 2026.
  2. news
    UCIe Consortium releases 2.0 specification supporting manageability system architecture and 3D packaging
    AutoTechInsight (Mobility Global), 21 Aug 2024. Accessed 21 Oct 2026.
  3. news
    [News] TSMC Set to Expand CoWoS Capacity to Record 75,000 Wafers in 2025, Doubling 2024 Output
    TrendForce, 2 Jan 2025. Accessed 21 Oct 2026.
  4. conference paper
    Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
    Yinxiao Feng, Kaisheng Ma. Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC 2022); arXiv preprint, 23 Mar 2022. Accessed 21 Oct 2026.
  5. preprint
    Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology
    Rahul Mathur, Chien-Ju Chao, Rossana Liu et al.. arXiv, 31 Jul 2020. Accessed 21 Oct 2026.

Revision history

3 changes since this profile was created.

Changes on 21 Oct 2026
Published on owner instruction (content loop iteration 24)f0449d2
Sources and claims re-checked against originalsfbb434c
Initial profile drafted from primary sources7e66249