Chips made with the next generation of EUV machines

How far is High-NA EUV lithography from routine use in high-volume chip production?

ASML's High-NA EUV scanners are now installed at chipmakers. Intel says it has entered high-volume manufacturing with them for a subset of Panther Lake processors, but it does not say which layers use them. Other chipmakers are still qualifying the tools. TSMC's public statements in 2026 say current EUV can carry its process through 2029, and a Digitimes headline reports a plan to adopt High-NA around 2030. Throughput and cost figures differ between sources.

AI illustration · Illustrative scene, not a photograph of the specific device or experiment.
WHERE WE AREPilots

Close. Early pilots are running in the real world.

High-NA tools have been shipped and installed, and Intel reports using them in high-volume manufacturing on a subset of one product family, without saying which layers. That is the company's own statement and was not checked against an independent source. Other chipmakers are still qualifying the tools, throughput figures conflict between sources, and no leading foundry has committed High-NA to its main logic nodes in the sources reviewed. This is a pilot stage, not a scaling one.

The tech tree

Everything recorded on Vrulum that this future needs, oldest foundations at the top and the goal at the bottom. Lines show what each step requires.

What it takes: Chips made with the next generation of EUV machines Unlocked Being researched Locked
  1. 2010Extreme ultraviolet (EUV) lithographyCommercial Unlocked.
  2. 2020Chiplets and advanced chip packagingCommercial Unlocked.
  1. 2024Prototype High-NA scanner available to chipmakersDone Unlocked.
  2. 2025First EXE:5200B scanner shipped for high-volume manufacturingDone Unlocked.
  3. 2025Acceptance testing completed at IntelDone Unlocked.
  4. 2026High-NA used in volume production for a subset of Panther Lake processors at one chipmakerDone Unlocked.
  5. 2026Installed base across several customersIn progress Being researched.
  6. 2026Single-exposure research patterning at 22 nm pitchDone Unlocked.
  7. Date not recordedFull qualification of the EXE:5200 at imecIn progress Being researched.
  8. Date not recordedAdoption by TSMC for leading logicNot started Locked.
  9. Date not recordedHyper-NA scanner at 0.75 NANot started Locked.
  1. GoalChips made with the next generation of EUV machinesGoalRequires: Extreme ultraviolet (EUV) lithography, Chiplets and advanced chip packaging, Prototype High-NA scanner available to chipmakers, First EXE:5200B scanner shipped for high-volume manufacturing, Acceptance testing completed at Intel, High-NA used in volume production for a subset of Panther Lake processors at one chipmaker, Single-exposure research patterning at 22 nm pitch, Full qualification of the EXE:5200 at imec, Installed base across several customers, Adoption by TSMC for leading logic, Hyper-NA scanner at 0.75 NA. Locked.

The road so far

5 of 9 steps done, 2 in progress.

  1. Done · Jul 2024Prototype High-NA scanner available to chipmakers

    imec says the first prototype 0.55 NA scanner, the TWINSCAN EXE:5000, is available to chipmakers, and that the first wafers have been exposed on it. The EXE:5000 is a prototype tool, not a production scanner. [5]

  2. Done · Jul 2025First EXE:5200B scanner shipped for high-volume manufacturing

    Bits&Chips reports that ASML shipped the EXE:5200B, which the article says is designed to support high-volume semiconductor manufacturing. The article gives a rating of 175 wafers per hour and a 60 per cent productivity gain over its predecessor. It says the buyer is almost certainly Intel, based on a 2022 purchase order, but does not confirm it. Reports give different dates for the first shipment. [3]

  3. Done · 16 Dec 2025Acceptance testing completed at Intel

    Bits&Chips reports that Intel has completed acceptance testing of the EXE:5200B. The test is reported to include 175 wafers per hour and 0.7 nanometre overlay accuracy. The article describes acceptance testing as a customer check of contract specifications under fab-like conditions, and gives no further details of the test setup. [4]

  4. Done · 23 Jul 2026High-NA used in volume production for a subset of Panther Lake processors at one chipmaker

    Intel's second-quarter 2026 earnings release says Intel Foundry has entered high-volume manufacturing for a subset of Core Ultra Series 3 (Panther Lake) processors using ASML's EXE High NA EUV technology. The release does not say which process layers use it. The claim is Intel's own and was not checked against an independent source. [2]

  5. Done · 15 Sept 2026Single-exposure research patterning at 22 nm pitch

    imec and partners report that a High-NA single-print step can pattern logic structures down to 22 nm pitch and vias at 28 nm centre-to-centre. The 22 nm pattern fidelity was shown on e-test structures. The article reports no yield figures for these results and says future work will drive yield improvement. [6]

  6. In progressFull qualification of the EXE:5200 at imec

    imec expects the EXE:5200 to be fully qualified by the fourth quarter of 2026. This is a target in a 2026 imec press release, as reported by TrendForce. It is not a result yet. [7]

  7. In progress · Sept 2026Installed base across several customers

    TrendForce, citing Economic Daily News, reports that 10 High-NA systems are running at four customers worldwide, with three more being shipped and installed. The report does not say which four customers these are. These counts come from press reports and have not been checked against ASML disclosures. [8]

  8. Not startedAdoption by TSMC for leading logic

    TSMC's deputy co-COO Kevin Zhang said at the 2026 Technology Symposium, as reported in April 2026, that TSMC has no plans to buy ASML's High-NA tool and can keep benefiting from current EUV through 2029. A Digitimes report dated 15 October 2026 has a headline saying TSMC plans to adopt High-NA in 2030. The article is paywalled and only the headline was seen. [9][10]

  9. Not startedHyper-NA scanner at 0.75 NA

    Martin van den Brink (ASML) showed a roadmap slide with Hyper-NA at 0.75 NA around 2030, in a May presentation at imec's ITF World, as reported by EE Times. ASML told EE Times that this is his vision and that feasibility studies are ongoing. The sources reviewed show no system built. [11]

Why it matters

The finest layers of the most advanced chips are printed with EUV. If High-NA can run in routine production, chipmakers could print finer features with fewer steps, which affects how fast chip density can keep rising. Throughput and cost decide whether it spreads beyond a few large buyers.

What stands in the way

  • Throughput is not settled. ASML rates the EXE:5200B at 175 wafers per hour. A TrendForce report from 1 September 2026, citing TechNews, gives 135 wafers per hour from acceptance testing. The sources reviewed do not reconcile the two figures.
  • Cost is very high. Electronics Weekly puts a High-NA scanner at about 350 million US dollars. TrendForce quotes Reuters at roughly 400 million US dollars. The sources reviewed do not reconcile the two figures.
  • High-NA's exposure field is half the size of the NXE field, according to ASML's own statement. The sources reviewed do not quantify how this affects throughput.
  • Qualification at most chipmakers is still in progress. imec's full-qualification date for the EXE:5200 is a target for the fourth quarter of 2026.
  • Research patterning at 22 nm pitch was shown on e-test structures, not production wafers. Yield on production layers has not been reported.
  • Hyper-NA at 0.75 NA is at feasibility stage. imec says it will depend on industry demand and on overcoming open technical problems.

Published forecasts

What others have predicted. These are their estimates, not ours.

WhoForecastTimeframeMade
Steven Scheer (imec)Insertion of High-NA EUV in high-volume manufacturing is expected in 2025 to 2026, first in logic chips of the 14A generation. Partly met: Intel reports volume use on a subset of processors in 2026, but the sources do not show 14A volume production. [5]2025–202612 Jul 2024
imecThe EXE:5200 will be fully qualified by the fourth quarter of 2026. [7]202619 Mar 2026
C.C. Wei (TSMC chairman and CEO)TSMC plans to adopt High-NA EUV in 2030, according to the headline of a Digitimes report that names Wei as CEO. The article body is paywalled and was not available to review. [10]203015 Oct 2026
Martin van den Brink (ASML)Hyper-NA at 0.75 NA is around 2030, as shown on a roadmap slide in a May presentation. ASML said this is his vision and that feasibility studies are ongoing. [11]20306 Dec 2024

Signals to watch

  • imec confirming that the EXE:5200 is fully qualified, as it has said it expects by the fourth quarter of 2026.
  • Public throughput figures for the EXE:5200B in customer fabs, and whether they reach the 175 wafers per hour rating.
  • Intel naming which process layers use High-NA, and whether 14A risk production starts as Bits&Chips reports it is planned for 2027.
  • TSMC naming a process node that uses High-NA, in place of the current statements about extending standard EUV.
  • ASML or a customer publishing installed-base counts for High-NA systems that can be checked against ASML's own reports.
  • A dated plan from ASML for Hyper-NA tools, beyond feasibility studies.

Sources

  1. company announcement
    5 things you should know about High NA EUV lithography
    Christine Middleton. ASML, 25 Jan 2024.
  2. company announcement
    Intel Reports Second-Quarter 2026 Financial Results
    Intel Corporation, via the US Securities and Exchange Commission, 23 Jul 2026.
  3. news
    ASML ships first high-NA EUV production scanner
    Paul van Gerven. Bits&Chips, 23 Jul 2025.
  4. news
    Intel completes acceptance testing of ASML's EXE:5200B high-NA EUV scanner
    Bits&Chips, 16 Dec 2025.
  5. other
    Entering the High NA EUV Lithography era
    imec, 12 Jul 2024.
  6. news
    Imec demoes 22nm pitch and 28nm vias on single-print High NA step
    Electronics Weekly, 15 Sept 2026.
  7. news
    imec secures ASML's most advanced EXE:5200 High-NA EUV for sub-2nm; 4Q26 qualification target
    TrendForce, 19 Mar 2026.
  8. news
    ASML advances High-NA EUV toward high-volume manufacturing as 10 systems reportedly go live at 4 customers
    TrendForce, 1 Sept 2026.
  9. news
    TSMC introduces A13 node; says no need for high-NA through 2029
    Electronics Weekly, 23 Apr 2026.
  10. news
    TSMC CEO says profitability has no ceiling, plans High-NA EUV adoption in 2030
    Monica Chen. Digitimes, 15 Oct 2026.
  11. news
    ASML aims for Hyper-NA EUV, shrinking chip limits
    Alan Patterson. EE Times, 6 Dec 2024.

Last reviewed 21 Oct 2026.