Optical interconnects and co-packaged optics

In plain language

Large AI data centres move huge volumes of data between processors, switches and memory. Most of that traffic still travels as electrical signals along copper wires, and the signal weakens over distance, so power-hungry circuits have to boost and clean it up on the way.

Co-packaged optics moves the conversion from electricity to light much closer to the chip. The optical engines sit in the same package as the switch or processor, so the electrical wires become very short, and the data leaves the package as light along fibre. Demonstrations in the lab and at trade shows have shown this working, but the approach is still early in becoming a mass-produced product.

Technical explanation

In a conventional switch, the switch chip sends data over electrical links, called SerDes, to pluggable optical modules at the front panel. Tian and colleagues (2024) note that pluggable optics are driven by wires that are usually a few inches long. Tan and colleagues (2023) state that co-packaged optics shortens the SerDes distance significantly, which greatly reduces the power needed for the electrical part of the link. VCSEL-based designs remain at the research and development stage (Tian and colleagues, 2024).

Power per bit is the main metric. Tian and colleagues quote Broadcom data suggesting that pluggable modules use about 15 to 20 pJ/bit, against about 5 to 10 pJ/bit for co-packaged optics. Individual demonstrations report lower figures. Tian and colleagues cite an Intel ISSCC 2024 link with a system power consumption of 1.3 pJ/bit, and an IBM MOTION transceiver at 4 pJ/bit at its maximum speed. Tan and colleagues give a target of below 5 pJ/bit for an Intel and Ayar Labs optical I/O design. This is an aim rather than a measured result. Tu and colleagues (2019) report a 32 by 32 silicon photonic switch fabric at about 0.8 pJ/bit for a 100 Gb/s light path, when the switch cell power is below 5 mW, as stated by the authors of their own device.

The external laser is a significant power cost. Tan and colleagues estimate about 18 W for the external laser source of a 6.4 Tbit/s tile, under an assumed configuration with a wall-plug efficiency of about 0.3. Thermal management is also difficult. A standards working group simulation, cited by Tian and colleagues, estimates a switch chip temperature of 151.76 °C at 5 m/s airflow with 16 CPO modules, which the authors say makes normal operation nearly impossible.

What the evidence says

Each statement is typed by the strength of its evidence and linked to the source that supports it.

Limitations and open problems

• Most power-per-bit figures come from single lab demonstrations or vendor data. The reviews cited here do not provide independently measured system-level savings.
• Thermal management is a serious constraint. The simulated 151.76 °C switch chip temperature cited by Tian and colleagues is a simulation result, not a measured one.
• Large-scale light sources are not yet mature. Tian and colleagues report that no stable, reliable large-scale VCSEL array exists at 56 GBaud. Tan and colleagues report that fibre coupling and light source integration are the main fabrication challenges for CPO chips.
• Waveguide and coupling losses cut into the power budget. Tan and colleagues report an extra 3 dB/cm loss in a standard strip waveguide with 50 mW injected.
• Standardisation is still in development. Tan and colleagues (2023) describe external laser source standardisation work under OIF.
• The Cisco demonstration reports system power savings only as 'up to' values, with no measured figures in the post (Cisco, 2023).

Possible future uses

Timeline

1. 13 Jan 2019A review of silicon photonic switches reports a 32 by 32 switch fabric at about 0.8 pJ/bit for a 100 Gb/s light path, under the conditions stated by its authors. Sources: [3]
2. 2021Intel and Ayar Labs demonstrate a multi-chip package reaching 8 Tbps, as reported in a 2024 review. Sources: [1]
3. 7 Mar 2023Cisco demonstrates a co-packaged optics router prototype at OFC 2023 driving 64 x 400G, compared against a pluggable-optics baseline. Sources: [4]
4. 2024Intel's ISSCC 2024 work reports a 4 x 64 Gb/s link at 1.3 pJ/bit, as reported in a 2024 review. Sources: [1]

Futures this could help bring about

How far away?

Computers built from mix-and-match chiplets

Engineering prototypes · 4 of 7 steps done

How far away?

Computers that calculate with light in data centres

Engineering prototypes · 5 of 8 steps done

How far away?

Internet cables that carry light through air

Pilots · 2 of 6 steps done

Related breakthroughs

• Experimental 400 Gb/s single-fibre transceiver built on a SiON optical interposer (9 Feb 2026)

Glossary

Co-packaged optics (CPO)

Optical engines placed in the same package as a switch or processor chip, so that the electrical links between them are very short.

SerDes

Serialiser-deserialiser circuits that convert parallel data into a fast serial stream for transmission over an electrical link.

Pluggable optical module

A removable optical transceiver that plugs into the front panel of a switch or server.

pJ/bit

Picojoules of energy used to move one bit of data; lower values mean more efficient links.

Sources

1. review article
   Progress in Research on Co-Packaged Optics
   Wenchao Tian, Huahua Hou, Haojie Dang et al.. Micromachines (MDPI), 29 Sept 2024. DOI: 10.3390/mi15101211. Accessed 21 Oct 2026.
2. review article
   Co-packaged optics (CPO): status, challenges, and solutions
   Min Tan, Jiang Xu, Siyang Liu et al.. Springer (Frontiers of Optoelectronics), 20 Mar 2023. DOI: 10.1007/s12200-022-00055-y. Accessed 21 Oct 2026.
3. review article
   State of the Art and Perspectives on Silicon Photonic Switches
   Xin Tu, Chaolong Song, Tianye Huang et al.. Micromachines (MDPI), 13 Jan 2019. DOI: 10.3390/mi10010051. Accessed 21 Oct 2026.
4. company announcement
   Cisco Demonstrates Co-packaged Optics (CPO) System at OFC 2023
   Anthony Torza. Cisco Systems (blog), 7 Mar 2023. Accessed 21 Oct 2026.

Revision history

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