Computers built from mix-and-match chiplets

How far are we from processors built from chiplets made by different companies?

The UCIe standard for linking chiplets has reached version 3.0. The Consortium describes the standard as enabling interoperability between chiplets, but the sources reviewed do not show that the specification by itself lets chiplets from different silicon vendors be combined in one package. In 2026 Intel and Cadence showed chiplets that each company had designed, linked together on a test chip, which the UCIe Consortium describes as the industry's first live UCIe-S interoperability demonstration. The sources reviewed do not show a commercial processor that mixes chiplets from different makers. Advanced packaging capacity, multi-stage testing, and compliance and interoperability testing are the main open issues.

AI illustration · Illustrative scene, not a photograph of the specific device or experiment.
WHERE WE AREEngineering prototypes

Getting closer. Prototypes exist, but not in real-world use.

The UCIe standard has been published through version 3.0, and cross-vendor interoperability has been shown, but only on a test chip at a 2026 event. The sources reviewed do not show a commercial processor that combines chiplets from different makers. The stage is therefore engineering prototype. Advanced packaging capacity is tight, and testing has to be done in more stages as packages get denser.

The tech tree

Everything recorded on Vrulum that this future needs, oldest foundations at the top and the goal at the bottom. Lines show what each step requires.

What it takes: Computers built from mix-and-match chiplets Unlocked Being researched Locked
  1. 2017Asteroid miningResearch and prototypes Being researched.
  1. 2014In-space manufacturingResearch and prototypesRequires: Asteroid mining. Being researched.
  1. 1964Reusable launch vehiclesPilot and early commercialRequires: In-space manufacturing. Unlocked.
  1. 2023Space-based solar powerResearch and prototypesRequires: Reusable launch vehicles, In-space manufacturing. Being researched.
  1. 2022Orbital data centresResearch and prototypesRequires: Space-based solar power, Reusable launch vehicles. Being researched.
  1. 2017Photonic computing for AIResearch and prototypes Being researched.
  2. 2019Optical interconnects and co-packaged opticsResearch and prototypesRequires: Orbital data centres. Being researched.
  3. 2020Chiplets and advanced chip packagingCommercial Unlocked.
  1. 2022Consortium launched to standardise chiplet connectionsDone Unlocked.
  2. 2024Standard extended to 3D packaging and system managementDone Unlocked.
  3. 2025Compliance and interoperability testing in placeIn progress Being researched.
  4. 2025Faster links published in version 3.0Done Unlocked.
  5. 2026Cross-vendor interoperability shown on a test chipDone Unlocked.
  6. 2026Advanced packaging capacity for multi-chiplet chipsIn progress Being researched.
  7. Date not recordedProcessors in volume that mix chiplets from different makersNot started Locked.
  1. GoalComputers built from mix-and-match chipletsGoalRequires: Chiplets and advanced chip packaging, Optical interconnects and co-packaged optics, Photonic computing for AI, Consortium launched to standardise chiplet connections, Standard extended to 3D packaging and system management, Faster links published in version 3.0, Cross-vendor interoperability shown on a test chip, Compliance and interoperability testing in place, Advanced packaging capacity for multi-chiplet chips, Processors in volume that mix chiplets from different makers. Locked.

The road so far

4 of 7 steps done, 2 in progress.

  1. Done · 2 Mar 2022Consortium launched to standardise chiplet connections

    The UCIe Consortium's launch announcement, dated 2 March 2022, says leaders in semiconductors, packaging, IP, foundries and cloud services joined to standardise the chiplet ecosystem. The Consortium's press release page lists a 1.1 specification released on 8 August 2023. [1]

  2. Done · 6 Aug 2024Standard extended to 3D packaging and system management

    Version 2.0 was released on 6 August 2024. Its release title describes a manageability system architecture and 3D packaging support. [1]

  3. Done · 5 Aug 2025Faster links published in version 3.0

    Version 3.0 was released on 5 August 2025. It supports 48 and 64 GT/s, against 32 GT/s in version 2.0, and the Consortium says it is fully backward compatible with all previous UCIe specifications. Sideband reach is extended to 100 mm. These are the Consortium's own claims, reported by Design And Reuse. [2][1]

  4. Done · Mar 2026Cross-vendor interoperability shown on a test chip

    At Chiplet Summit 2026, Intel and Cadence showed a test chip called Cameron Creek. It linked chiplets that each company had designed independently, using 16G UCIe-S PHY IP. The UCIe Consortium's account says the demonstration validated cross-vendor interoperability and UCIe Interoperability Testing. This was one test chip, not a product, and no independent test report was found. [3]

  5. In progress · 20 Feb 2025Compliance and interoperability testing in place

    In February 2025 the Consortium's tutorial recap said one of the primary concerns is the need for robust compliance and interoperability testing frameworks. Cadence highlighted its collaboration with Intel to achieve UCIe compliance and described interoperability testing through pre-silicon simulation. Siemens reported a pilot project with Alphawave Semi and Ayar Labs, using verification IP for compliance and interoperability testing in simulation. The sources reviewed do not show a published compliance programme with a list of chiplets that have passed it. [4]

  6. In progress · 15 Jun 2026Advanced packaging capacity for multi-chiplet chips

    TrendForce, reporting on 15 June 2026, gives an estimate that TSMC's monthly CoWoS capacity could reach 120,000 to 140,000 wafers in 2026. These are market estimates, not official TSMC figures. Institutional investors expected the supply gap to narrow from about 20% to about 10% by the end of 2026. [5]

  7. Not startedProcessors in volume that mix chiplets from different makers

    The sources reviewed do not show a commercial processor or accelerator that combines chiplets from different makers in volume production.

Why it matters

A chiplet is a smaller piece of a chip that is joined with other pieces in one package. If chiplets from different makers can be connected through a shared standard, a chip designer could pick the best part from each supplier instead of designing every part in-house. That could lower cost and shorten design time. Testing, packaging supply and proof of compliance would decide whether that choice works in practice.

What stands in the way

  • No commercial processor that mixes chiplets from different makers is shown in the sources reviewed. Cross-vendor work so far is at demonstration stage.
  • Testing has to happen earlier and in more stages. Teradyne argues for 'known-good everything', meaning metrology, automated test and system-level test together. It also says testing now has to happen on unpackaged modules through C4 bumps, which needs new prober designs.
  • Compliance and interoperability testing is still a key concern. The UCIe Consortium's own 2025 tutorial recap said so, and the sources reviewed do not show a published list of chiplets that have passed UCIe compliance testing.
  • Advanced packaging capacity is tight. The capacity figures found are market estimates, not official TSMC numbers, and investors expected the supply gap to narrow to about 10% by the end of 2026.

Published forecasts

What others have predicted. These are their estimates, not ours.

WhoForecastTimeframeMade
TSMC (as reported by Reuters and quoted by TrendForce)CoWoS advanced packaging capacity is projected to grow at a compound annual rate of more than 80% from 2022 to 2027. TSMC made this projection at its Taiwan Technology Symposium in May. TrendForce's article is dated 15 June 2026 and does not state the symposium's year, so 2026 is inferred. It is a company projection about capacity, not a forecast about chiplets from different makers. [5]2027May 2026

Signals to watch

  • A processor on sale whose product pages name chiplets from two or more different makers.
  • A published list of chiplets that have passed UCIe compliance testing, or a compliance programme with named participants.
  • Further joint demonstrations of cross-vendor UCIe links beyond the Intel and Cadence test chip.
  • TSMC wafers-per-month figures for CoWoS in its own investor materials, in place of market estimates.

Sources

  1. company announcement
    UCIe Consortium press releases
    UCIe Consortium, 5 Aug 2025.
  2. news
    UCIe Consortium Introduces 3.0 Specification With 64 GT/s Performance and Enhanced Manageability
    Design And Reuse, 5 Aug 2025.
  3. company announcement
    Chiplet Summit 2026: UCIe Momentum Across a Growing Ecosystem
    UCIe Consortium, Mar 2026.
  4. company announcement
    Unlocking the Future of Chiplet Integration: A Recap of the UCIe Chiplet Summit Tutorial
    UCIe Consortium, 20 Feb 2025.
  5. news
    TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026
    TrendForce, 15 Jun 2026.
  6. company announcement
    AI Chiplet Architectures Redefining Test Insertions
    Teradyne, 27 Jul 2026.

Last reviewed 21 Oct 2026.